#-----------------------------------------------------------------------
# Tests for an instruction with vector-vector operors
#-----------------------------------------------------------------------
#include "riscv_test.h"
#undef RVTEST_RV64S
#define RVTEST_RV64S RVTEST_RV32M
#define __MACHINE_MODE

# See LICENSE for license details.
# Test illegal instruction trap.
#
#*****************************************************************************
# vor.S
#-----------------------------------------------------------------------------
#
#include "riscv_test.h"
#include "test_macros.h"
#include "test_register.h"

#ifdef N600_CFG_HAS_VPU
#ifdef N600_CFG_VPU_ELEN_64
#ifndef N600_CFG_HAS_ONLY_VCAU
RVTEST_RV64U
RVTEST_CODE_BEGIN

.align 2
.option norvc

li TESTNUM, 2
  #-------------------------------------------------------------
  # Initialization
  #-------------------------------------------------------------

  #enable vpu
  li x1, 0x200
  csrs mstatus, x1

  li x11, 32
  vsetvli x10, x11, e32, m1
  li x0, 8
  li x0, 8
  li x0, 8
  li x0, 8
  vmv.v.i v0 , 0
  vmv.v.i v1 , 0
  vmv.v.i v2 , 0
  vmv.v.i v3 , 0
  vmv.v.i v4 , 0
  vmv.v.i v5 , 0
  vmv.v.i v6 , 0
  vmv.v.i v7 , 0
  vmv.v.i v8 , 0
  vmv.v.i v9 , 0
  vmv.v.i v10, 0
  vmv.v.i v11, 0
  vmv.v.i v12, 0
  vmv.v.i v13, 0
  vmv.v.i v14, 0
  vmv.v.i v15, 0
  vmv.v.i v16, 0
  vmv.v.i v17, 0
  vmv.v.i v18, 0
  vmv.v.i v19, 0
  vmv.v.i v20, 0
  vmv.v.i v21, 0
  vmv.v.i v22, 0
  vmv.v.i v23, 0
  vmv.v.i v24, 0
  vmv.v.i v25, 0
  vmv.v.i v26, 0
  vmv.v.i v27, 0
  vmv.v.i v28, 0
  vmv.v.i v29, 0
  vmv.v.i v30, 0
  vmv.v.i v31, 0

test_start:

#*****************************************************************************
# vor.vv( testnum, inst, vl, sew, mul, result, val2, val1 );Bitwise
#-----------------------------------------------------------------------------
  #----------------------------------------------------------------------
  # TEST_VV_OP_8
  #----------------------------------------------------------------------
    TEST_VV_OP(sew8vv_2 , vor.vv, 16, 8, 1, 0x11, 0x00, 0x11 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VVvm_OP(sew8vv_3 , vor.vv, 16, 8, 1, 0x00, 0x20,  0x11 );
    TEST_VV_OP(sew8vv_4 , vor.vv, 128, 8, 8, 0x12, 0x12, 0x02 );
    TEST_VV_OP(sew8vv_5 , vor.vv, 128, 8, 8, 0x17, 0x12, 0x07 );

  #----------------------------------------------------------------------
  # TEST_VV_OP_16
  #----------------------------------------------------------------------
    TEST_VV_OP(sew16vv_2 , vor.vv, 8, 16, 1, 0x0011, 0x0000, 0x0011 );
    TEST_VV_OP(sew16vv_3 , vor.vv, 8, 16, 1, 0x0031, 0x0020, 0x0011 );
    TEST_VV_OP(sew16vv_4 , vor.vv, 64, 16, 8, 0x0012, 0x0012, 0x0002 );
    TEST_VV_OP(sew16vv_5 , vor.vv, 64, 16, 8, 0x0017, 0x0012, 0x0007 );

  #----------------------------------------------------------------------
  # TEST_VV_OP_32
  #----------------------------------------------------------------------
    TEST_VV_OP(sew32vv_2 , vor.vv, 4, 32, 1, 0x00000011, 0x00000000, 0x00000011 );
    TEST_VV_OP(sew32vv_3 , vor.vv, 4, 32, 1, 0x00000031, 0x00000020, 0x00000011 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VVvm_OP(sew32vv_4 , vor.vv, 32, 32, 8, 0x00000000, 0x00000012, 0x00000002 );
    TEST_VV_OP(sew32vv_5 , vor.vv, 32, 32, 8, 0x00000017, 0x00000012, 0x00000007 );

  #----------------------------------------------------------------------
  # TEST_VV_OP_64
  #----------------------------------------------------------------------
    TEST_VV_OP(sew64vv_2 , vor.vv, 2, 64, 1, 0x0000000000000011, 0x0000000000000000, 0x0000000000000011 );
    TEST_VV_OP(sew64vv_3 , vor.vv, 2, 64, 1, 0x0000000000000031, 0x0000000000000020, 0x0000000000000011 );
    TEST_VV_OP(sew64vv_4 , vor.vv, 16, 64, 8, 0x0000000000000012, 0x0000000000000012, 0x0000000000000002 );
    TEST_VV_OP(sew64vv_5 , vor.vv, 16, 64, 8, 0x0000000000000017, 0x0000000000000012, 0x0000000000000007 );


#*****************************************************************************
# vor.vx
#-----------------------------------------------------------------------------
  #----------------------------------------------------------------------
  # TEST_VX_OP_8
  #----------------------------------------------------------------------
    TEST_VX_OP(sew8vx_2 , vor.vx, 16, 8, 1, 0x11, 0x00, 0x11 );
    TEST_VX_OP(sew8vx_3 , vor.vx, 16, 8, 1, 0x31, 0x20,  0x11 );
    TEST_VX_OP(sew8vx_4 , vor.vx, 128, 8, 8, 0x12, 0x12, 0x02 );
    TEST_VX_OP(sew8vx_5 , vor.vx, 128, 8, 8, 0x17, 0x12, 0x07 );

  #----------------------------------------------------------------------
  # TEST_VX_OP_16
  #----------------------------------------------------------------------
    TEST_VX_OP(sew16vx_2 , vor.vx, 8, 16, 1, 0x0011, 0x0000, 0x0011 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VXvm_OP(sew16vx_3 , vor.vx, 8, 16, 1, 0x0000, 0x0020, 0x0011 );
    TEST_VX_OP(sew16vx_4 , vor.vx, 64, 16, 8, 0x0012, 0x0012, 0x0002 );
    TEST_VX_OP(sew16vx_5 , vor.vx, 64, 16, 8, 0x0017, 0x0012, 0x0007 );

  #----------------------------------------------------------------------
  # TEST_VX_OP_32
  #----------------------------------------------------------------------
    TEST_VX_OP(sew32vx_2 , vor.vx, 4, 32, 1, 0x00000011, 0x00000000, 0x00000011 );
    TEST_VX_OP(sew32vx_3 , vor.vx, 4, 32, 1, 0x00000031, 0x00000020, 0x00000011 );
    TEST_VX_OP(sew32vx_4 , vor.vx, 32, 32, 8, 0x00000012, 0x00000012, 0x00000002 );
    TEST_VX_OP(sew32vx_5 , vor.vx, 32, 32, 8, 0x00000017, 0x00000012, 0x00000007);

  #----------------------------------------------------------------------
  # TEST_VX_OP_64
  #----------------------------------------------------------------------
    TEST_VX_OP(sew64vx_2 , vor.vx, 2, 64, 1, 0x0000000000000011, 0x0000000000000000, 0x0000000000000011 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VXvm_OP(sew64vx_3 , vor.vx, 2, 64, 1, 0x0000000000000000, 0x0000000000000020, 0x0000000000000011 );
    TEST_VX_OP(sew64vx_4 , vor.vx, 16, 64, 8, 0x0000000000000012, 0x0000000000000012, 0x0000000000000002 );
    TEST_VX_OP(sew64vx_5 , vor.vx, 16, 64, 8, 0x0000000000000017, 0x0000000000000012, 0x0000000000000007 );


#*****************************************************************************
# vor.vi
#-----------------------------------------------------------------------------
  #----------------------------------------------------------------------
  # TEST_VI_OP_8
  #----------------------------------------------------------------------
    TEST_VI_OP(sew8vi_2 , vor.vi, 16, 8, 1, 0x11, 0x11, 0x00 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VIvm_OP(sew8vi_3 , vor.vi, 16, 8, 1, 0x00, 0x18,  0x0f );
    TEST_VI_OP(sew8vi_4 , vor.vi, 128, 8, 8, 0x12, 0x12, 0x02 );
    TEST_VI_OP(sew8vi_5 , vor.vi, 128, 8, 8, 0x17, 0x12, 0x07 );

  #----------------------------------------------------------------------
  # TEST_VI_OP_16
  #----------------------------------------------------------------------
    TEST_VI_OP(sew16vi_2 , vor.vi, 8, 16, 1, 0x0011, 0x0011, 0x0000 );
    TEST_VI_OP(sew16vi_3 , vor.vi, 8, 16, 1, 0x001f, 0x0018, 0x000f );
    TEST_VI_OP(sew16vi_4 , vor.vi, 64, 16, 8, 0x0012, 0x0012, 0x0002 );
    TEST_VI_OP(sew16vi_5 , vor.vi, 64, 16, 8, 0x0017, 0x0012, 0x0007 );

  #----------------------------------------------------------------------
  # TEST_VI_OP_32
  #----------------------------------------------------------------------
    TEST_VI_OP(sew32vi_2 , vor.vi, 4, 32, 1, 0x00000011, 0x00000011, 0x00000000 );
    li x12, 0x0000;
    vmv.v.x v0 , x12;
    TEST_VIvm_OP(sew32vi_3 , vor.vi, 4, 32, 1, 0x00000000, 0x00000018, 0x0000000f );
    TEST_VI_OP(sew32vi_4 , vor.vi, 32, 32, 8, 0x00000012, 0x00000012, 0x00000002 );
    TEST_VI_OP(sew32vi_5 , vor.vi, 32, 32, 8, 0x00000017, 0x00000012, 0x00000007 );

  #----------------------------------------------------------------------
  # TEST_VI_OP_64
  #----------------------------------------------------------------------
    TEST_VI_OP(sew64vi_2 , vor.vi, 2, 64, 1, 0x0000000000000011, 0x0000000000000011, 0x0000000000000000 );
    TEST_VI_OP(sew64vi_3 , vor.vi, 2, 64, 1, 0x000000000000001f, 0x0000000000000018, 0x000000000000000f );
    TEST_VI_OP(sew64vi_4 , vor.vi, 16, 64, 8, 0x0000000000000012, 0x0000000000000012, 0x0000000000000002 );
    TEST_VI_OP(sew64vi_5 , vor.vi, 16, 64, 8, 0x0000000000000017, 0x0000000000000012, 0x0000000000000007 );




 TEST_PASSFAIL
.align 8

illegal_instruction_horler_pit:
        csrr a0, mbadaddr
        lw ra, 18*4(sp)
        lw t6, 17*4(sp)
        lw t5, 16*4(sp)
        lw t4, 15*4(sp)
        lw t3, 14*4(sp)
        lw t2, 13*4(sp)
        lw t1, 12*4(sp)
        lw t0, 11*4(sp)
        lw a7, 10*4(sp)
        lw a6, 9*4(sp)
        lw a5, 8*4(sp)
        lw a4, 7*4(sp)
        lw a3, 6*4(sp)
        lw a1, 4*4(sp)
        lw a0, 3*4(sp)
        csrw mcause, a1
        addi a0,a0,0x08
        csrw mepc, a0
        lw a0, 1*4(sp)
        lw a1, 0*4(sp)
        addi sp, sp, 20*4
        mret

RVTEST_CODE_END

  .data
RVTEST_DATA_BEGIN

  TEST_DATA

RVTEST_DATA_END
.align 2
.option norvc
#endif
#endif
#endif

#if (!defined N600_CFG_HAS_VPU) || (!defined N600_CFG_VPU_ELEN_64) || (defined N600_CFG_HAS_ONLY_VCAU)
RVTEST_RV64M
RVTEST_CODE_BEGIN

j pass

TEST_PASSFAIL
RVTEST_CODE_END
  .data
RVTEST_DATA_BEGIN
  TEST_DATA

RVTEST_DATA_END

#endif
